Krishan we had discussed many many times and @Fox.FAE had also repeated the same result on his side. There is nothing to do with startup.
The bump and the poor load and line is the converter itself.
And with all due respect as a FAE you should understand the purpose of EVM or EVB.
EVB or EVM itself is a reference ground to test the chip on a specific output from the start.
So in this case 3.3V for MP(Q)4470 EVM.
However, replacing the passive component and modifying the output without alternating the PCB layout (which somehow the EVM or EVB layout is considered as the recommended layout) is not helping on the current problem. Why it is? Because FOX also proposing a repeated issues on his side. So you are telling us that the chip is what having issue.
So in real situation do product used the EVM? No because we are still going to transfer the layout as much as we could to the final product layer stacks BOM alternates all result in a different result.
So allow me to say in such way EVM or EVB is what internal company used the most not (well experienced) customers because taking out the layout parameters from the equation is just not the case.
You can do all charming results on EVM or EVB but once the case is transferred to real product layout you are going to face the new sets of issues (aka small alterations result in huge modifications).
What do this mean? Unstable system and very poor adaptation.
And lets be real again, MP(Q)4470 testing report do not show the load and line regulation on any 5V 12V or above. 3.3V of cause datasheet is giving out stable and various of data so no issue on that. All we are concerning and discussing is all about 5V or above cases.
And we only see efficiency curves and claims but no actual data on load, line and various of waveform to support.
And on top of that it is necessary to say that these data are paramount as commonly used power rails are those range.
Bests,
Brian