MPQ4470 Cannot Regulate

DC-DC Power Converters
1

Dear MPS,

This is Brian and had encountered issue on MPQ4470 converter.

The design is as follows:

image
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The compensation from the MPS DC/DC Designer proposed two type RAMP1/2.
I had tried both compensation methods.

A)
RAMP1 show a regulation on 12V but the voltage is anormal.
When no load condition the output is set 12.0V which is good.
However once the converter is loaded with 100mA and the voltage immediately jump to 12.7V.
Along the constant current load is increase the voltage drop to 11.85V @ 3.5A.

B)
RAMP2 show no regulation and output is not even met the 12V point and only 6.5V is measured.

Please MPS assist on such abnormal behavior.

Bests,
Brian

2

@MPSnow_Nouman @Fox.FAE @MPSNow_Saurabh @MPSNow_Yu

Dear MPS,

This is Brian, I had strong investigation on the MPQ4470 sync-buck design.
According to the tool DCDC Designer 3.20 proposed design.
The converter is not able to converge and could not regulate to the target design voltage.
However when cross checked with MPSmart the design on simulator could converge and met the set point voltage.

Please MPS investigate the DCDC Designer tool is bugged or there are overflow etc.

Bests,
Brian

3

Hi,

Sorry for the late response.

I have used the DC-DC designer to calculate the parameter based on the customized application condition, the RAMP1/RAMP2 result is as shown in Fig.1 and Fig.2, it shows the result I get is quite different with the customer has, could you help confirm whether the customer used the latest version DC-DC designer? The version I am using is:
image

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Fig.1 v3.32 DC-DC designer RAMP1 calculated result

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Fig.2 v3.32 DC-DC designer RAMP2 calculated result

We will continue figuring out why Vout varies in your other questions.

Best,
Fox

4

@Fox.FAE

Ok you are proposing using the DCDC designer here.
Use those value and simulate via MPSmart and see if the design is converge or diverge.

In our current state the 5V 5A regulator after many many many computation and trail are able to hold the line and load regulation. And even loaded power on test.

But when comes to 12V case no matter how we try it will not converge and line and load regulation is completely unacceptable.

Bests,
Brian

5

Hi,

We are trying to help you get a stable system when the output=12V. Both software and hardware. Thanks for your waiting.

So your question now is you need to have a stable 12V output system and want to know why it is not stable. Am I correct?

Best,
Fox

6

@Fox.FAE

From my sim result the RAMP2 cases are not converging.
Cross confirm if you are having the same result.

Bests,
Brian

7

@Fox.FAE

I am not sure we are on the same page.
The converter with most reasonable RAMP configuration passive components value are all tried.
And yet we are not able to get a good line and load regulation.
But all trials are closed to 12V when tuned the R1 and R2 feedback resistor network.

Lets make things easier and only setting inductor to 4.7uH:
Inductor data as follows:
image

All other components are good to change and value replacement.
Based on 4.7uH please MPS help to provide a good line load configuration.
From computation the 140k freq resistor should able to run at 850kHz and within 4.7uH range.

Bests,
Brian

8

Well this seems like a pretty simple minded system the heart of it is a comparator hitting a one shot, or an input voltage reactive one-shot. You can build in in LTspice if you want and play with it.
the FB comparator needs ripple that has some time delay in order to work. When I built this with decent output caps, there wasn’t enough ripple to make the thing oscillate reliably. Adding ripple voltage from the switch node allows you to have both a low ripple output voltage and operation.

Can’t seem to upload a pdf of the sch

9

@jshannon

Are you trying to help or ?
MPSmart is what the official simulator.
All those steps are already done and we are discussing tools are not converging and real hardware performance is poor.

I cannot understand what you are proposing or suggesting.
COT is what the topology of this converter.

Bests,
Brian

10

Hi,

Sorry for the latency, about the mentioned question of MPQ4470, this is the follow-up.
Let us back to the customer original question, first.
#A RAMP1 show a regulation on 12V but the voltage is anormal.
When no load condition the output is set 12.0V which is good.
However once the converter is loaded with 100mA and the voltage immediately jump to 12.7V.
Along the constant current load is increase the voltage drop to 11.85V @ 3.5A.

We replaced the R9 in Fig.1 with a 470nF, we have observed that the output is regulated around 12V and we also saw oscillation occurs on SW as shown in Fig.2, which means the ripple injected on FB is not enough.
The poor line regulation may resulted from large injected ripple amp which result in the difference of Vo between PSM and CCM, however, the scenario is quite opposite with our test result which shows insufficient ripple injection.
Considering there is only one sch of RAMP2 has been given, could you help check what is the exactly sch of RAMP1 set?

#B RAMP2 show no regulation and output is not even met the 12V point.

Based on the parameter given by customer as shown in Fig,1, that using RAMP2, the test result shows that it could not output required 12V, only 6.5V, which is accordance with the theory and our test result, cause that RAMP type circuit the ripple injection circuit would introduce a DC voltage on FB too rather than only ripple, so when we using this type of injection circuit that with DC-block cap, we should take the res of injection circuit into consideration to design such res divider parameter.

And further, we have checked that our parameter designer would take above mentioned into consideration when designing the res divider.
image
Fig.1 Sch of default setup given by you
image
Fig.2 Oscillation on SW CH1:SW CH2:Vo CH3:io CH4:iL

Best,
Fox

11

@Fox.FAE

Okay there are a lot of information in your reply.

I will reply in two sections:

Section I:

My design is not simply follow the DCDC Design tool. Once I see the output is abnormal I tuned the bottom resistor of the feedback resistor and make the current larger and hences the ramp can be more stable and noise immune.
So I had tried the range of 3k to 5k rather than the MPS proposed 5k or above. This is very logical that when experiment no matter what 5k to 40k the load current will always unstable and output drop to 0 and lock out.

On top of that assumption, that is why the behavior is reversed.

Q

Based on the parameter given by customer as shown in Fig,1, that using RAMP2, the test result shows that it could not output required 12V, only 6.5V, which is accordance with the theory and our test result,

A

I just follow what DCDC Designer suggested from beginning of designing the 12V.
Open DCDC Designer enter 12V 5A and ~900khz to use 4.7uH in the allowed parts list.

The suggested value:
image

And redo by selecting RAMP2:
image

What result you get from DCDC Designer is what I had tried in the passed weeks.
Meantime, the DCDC Designer had updated before my post are started.
So result might have change a bit but I cannot see the proposed RAMP is valid and can achieve good result.

Section II:

I will make things more simple by just follow the document MPS that had posed and done.
“5A, 36V Synchronous Buck Converter
in a 3x4mm Package
Application Note
Prepared by Jens Hedrich
Jan. 19, 2015”

Link:https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Application%20Note/lang/en/sku/MP4470GL-Z/document_id/606/

image

You can see MPS had done a 12V design before and using 22uH I had tried to repeat this design by due to inductor parts on hands are limited to only 10uH and 15uH. I am not sure this is RAMP1 or RAMP2 design but I still cannot see this can be regulate normally when using RAMP2 nor RAMP1 configuration.

Based on this configuration the voltage will drop at the end of the PSM and jump up at the beginning of CCM and completed die after some point of the load current.

I cannot see why the measurement data can be achieved and repeated.

So please check if this data is repeatable on 10uH as 12V 500kHz do not require 22uH from theory.

Additional Comments:

Well MPS I do see all units are helping out by after 9 years of this product why there are no solution to settle 12V and 24V.
And so it is also proposing that the DCDC Design Tools are having trouble on real application.

Bests,
Brian

12

Hey Brian,

At the end of the day, the DC/DC designer tool is an approximation with wide simulation constrained limits. I have been following other cases but wanted to get back to you on this. Have you tested with the EVB?

With that being said here is a link to the EVB that we currently have: monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/EV4470-L-01A/document_id/3119/

Do the startup waveforms in this case coincide with the AE testing results that Fox has relayed back to you? If so, I would encourage alternative forms of testing like setting the EVB to your specific desired parts for further verification.

Best,
Krishan

13

@Krishan.FAE

Krishan we had discussed many many times and @Fox.FAE had also repeated the same result on his side. There is nothing to do with startup.
The bump and the poor load and line is the converter itself.

And with all due respect as a FAE you should understand the purpose of EVM or EVB.
EVB or EVM itself is a reference ground to test the chip on a specific output from the start.
So in this case 3.3V for MP(Q)4470 EVM.
However, replacing the passive component and modifying the output without alternating the PCB layout (which somehow the EVM or EVB layout is considered as the recommended layout) is not helping on the current problem. Why it is? Because FOX also proposing a repeated issues on his side. So you are telling us that the chip is what having issue.

So in real situation do product used the EVM? No because we are still going to transfer the layout as much as we could to the final product layer stacks BOM alternates all result in a different result.

So allow me to say in such way EVM or EVB is what internal company used the most not (well experienced) customers because taking out the layout parameters from the equation is just not the case.
You can do all charming results on EVM or EVB but once the case is transferred to real product layout you are going to face the new sets of issues (aka small alterations result in huge modifications).
What do this mean? Unstable system and very poor adaptation.

And lets be real again, MP(Q)4470 testing report do not show the load and line regulation on any 5V 12V or above. 3.3V of cause datasheet is giving out stable and various of data so no issue on that. All we are concerning and discussing is all about 5V or above cases.
And we only see efficiency curves and claims but no actual data on load, line and various of waveform to support.

And on top of that it is necessary to say that these data are paramount as commonly used power rails are those range.

Bests,
Brian

14

Hi Brian,

It seems there are a lot of moving pieces, operating conditions, test set-up, and desired results needed to take into account.

I recall in another thread you mentioned submitting a ticket but if you could kindly submit one again stating the issue you want resolved, the operating conditions, test set-up, and project information at MPSNow Support, we can better align.

At that time as well, we can set-up a call with local resources to have a better idea on the issue you’re seeing and perhaps even go through a demo of our EVB, modified at your desired output voltages to show the robustness of our device and that likely we need to fine-tune the design you originally implemented.

Let us know once you’ve submitted the ticket, along with the confirmation number, and we’ll work swiftly to help you resolve your issue. Thanks.

Regards,
Christian

15

@christian.cross

I would like to address that @Fox.FAE is helping out on this issue.
How many party is here I am a bit confused.
I would like to make sure Fox is going to work out the bump issue first.
At the same time, are Fox going to handle this issue or passed to other party?
Better on confirming that before I submit the ticket.
Meanwhile, Fox and our side is having common ground on the last proposed schematic, which is repeatable on Fox’s claims. But the bump is too puzzling, which is not addressed.

And Christian the goal here is not making a specific design but following the DCDC Designer proposed design from first place and have a workable design.
Even the latest proposed schematic from Fox is following the default DCDC Designer design the bump issue is still exist and way passed the acceptable range.

And to be honest that if a converter is so picky on the layout, and components.
I don’t think it is good to use it from first place.

Don’t get me wrong.
When a proper layout is used but the routing is offsetted closer or farther will introduce huge tuning.
Switch node routing between capacitor or next to the capacitor will introduce faulty design.
Using additional 0805 capacitor to allow switch node can be routed between capacitor and messing up BOM consolidation.
All these unreasonable layout and component requirement is what picky means.
Component got tolerations, and will aged along the usage.
Layout is subjected to density and rooms.
All these design constraints can easily mess up the MPS tuned design, and turning back support are going to create all kinds of headache.

Bests,
Brian

16

Apologies, I didn’t specify as to why I suggested an EVB / EVM.

You are correct in the sense as to the purposes of these boards as a reference and to showcase performance of a part.

However, as an FAE, the job involves using the EVB / EVM as a working reference and to change out components to replicate designs with different outputs, modes, and also to replicate issues as well. This is done to isolate issues that show up under consistent cases like layout, possible shorts, and component ratings (which in this case based on your findings are constrained).

But of course, as you said, the tuning with another layout differences all play a role. In this case, we will be looking forward to your ticket when it comes.

18

@Krishan.FAE @Fox.FAE

Had opened a ticket and got an Email but no responses are given from MPS.

Bests.
Brian