VINA/VINB UV error observed during start up

Hi,

  1. The read of register 0x00 is giving value 0x82. Is this correct? My understanding is that it should give value 0x80(as bits 1 and 2 are reserved bits with reset value of 0). This is the case we see if 0x00 is written with either 0x82 or 0x83.
    1. This is what i have in datasheet

    2. this is the version

  2. What should be written during HSS configuration to register 0x00 - IS it 0x80 or 0x81?
  3. Another behaviour we are seeing is that when 0x00 is written with value 0x82 - we are seeing that FT pin is LOW and register 0x05 has value 0x50 (VINa/VINB UV fault is present). IS a UV error expected during system start up?
  4. But when 0x00 is written with value 0x83 - we are seeing that FT pin is HIGH and register 0x05 has value 0x00 (VINa/VINB UV fault is NOT present)

Hi,

I need mainly answer for the below 3 questions, as below. You may ignore the UV questions.

  1. The read of register 0x00 is giving value 0x82. Is this correct? My understanding is that it should give value 0x80(as bits 1 and 2 are reserved bits with reset value of 0). This is the case we see if 0x00 is written with either 0x82 or 0x83.

    1. This is what i have in datasheet

      image

      image967×486 74.9 KB

    2. this is the version

      image

      image965×103 13.2 KB

  2. What should be written during HSS configuration to register 0x00 - IS it 0x80 or 0x81?

  3. Assume that there was a OV fault active. And after sometime, it became inactive. Once we write 1 to the bit FTCLR - it clears the status registers and sets the FT pin high, as the fault is no longer present. And once this happens, if any new error is detected after sometime in the same power cycle, the status registers and the FT pin will indicate the same as well. Is this understanding correct?