The MA782 Rev. 1.1 8/30/2021 datasheet, Figure 11 shows the SPI timing diagram for Mode 3.
Table 4: SPI Timing calls out tcsl - Time between /CS falling edge and SCLK falling edge - as 120ns Min.
What is the equivalent for SPI Mode 0? Because in Mode 0, the SCLK edge will be a rising edge!
The MA732 Rev 1.0 4/23/2019 datasheet, Figure 7 SPI timing diagram shows timing for Mode 3. And this time, the Tcsl is 80ns min.
What is the equivalent for SPI Mode 0?
What happens if I cannot meet this spec.?
For the MA782: