SPI interface on MA782 and MA732

The MA782 Rev. 1.1 8/30/2021 datasheet, Figure 11 shows the SPI timing diagram for Mode 3.

Table 4: SPI Timing calls out tcsl - Time between /CS falling edge and SCLK falling edge - as 120ns Min.

What is the equivalent for SPI Mode 0? Because in Mode 0, the SCLK edge will be a rising edge!

The MA732 Rev 1.0 4/23/2019 datasheet, Figure 7 SPI timing diagram shows timing for Mode 3. And this time, the Tcsl is 80ns min.

What is the equivalent for SPI Mode 0?

What happens if I cannot meet this spec.?

For the MA782:

Hi Harjit,
t(CSL) is just the minimum time between dropping CS and the beginning of the master clocking in data. So, for SPI mode 3, it would just be the min time between CS going active (low) and your first rising clock edge.
If that specification is not met, the result could be the MA missing your first SCLK transition and not seeing the first bit of data on MOSI or not transmitting over MISO until the next SCLK cycle.


@sensors.ted Thank you for the super quick response!

Can you comment about the timing for mode 0? Because in this case, there is no falling edge that tCSL refers to.


Mode 0 is essentially the same as Mode 3 except that the SCLK is inverted. So, you can use the same timing diagram, just invert the clock signal. In the case of M0, t(CSL) must be held before we see the first rising edge after CS is asserted.


Thank you. Makes sense.

Would be great if this can be captured in all the MA* products with SPI. I must have read the different datasheets at least a dozen times and I missed it until the last time.

All the best!