On your page, Virtex UltraScale+ Smallest Size Power Management Reference Design the block diagram shows a filter block between the DC output of a MPM module and the VIN of a VMGT supply. The VMGT’s must be under 10mVpp noise so I suspect that the purpose of the filter is to get the output noise of the MPM down below this value which also implies that without the filter, the noise may be above 10 mVpp. Can more details be shared on this filter circuit? Even better, can the design files for this reference design be made available? Of the Xilinx reference designs with available design files, I could not find mention of this filter.
Hi,
You are correct that the filter it to keep the noise below 10mVpp. Our article here(MPS Power Modules Offer A Compact and Ultra-Low Noise Solution for AMD Xilinx Zynq UltraScale+ RFSoC | Article | MPS) goes into further detail. In summary, a LC filter is used at the output to reduce the peaks.
Since this was a paper design, there are no schematic files, however each of the parts have datasheets with guidance on schematic and layout.
For further assistance on your design, you may contact mpsnow@monolithicpower.com.