Questions about Gate Driver for GaN FET in half bridge topology

Motor Drivers/Sensors
1
  1. I reviewed the specifications of gate driver MPQ1918 and written under topic of Bootstrap (BST) Clamping that in addition to new charging logic, there is also a clamp mechanism, as I quoted here from the datasheet on this subject :Bootstrap (BST) Clamping:" In addition, the electrostatic discharge (ESD) between BST and SW also clamps VBST-SW such that it does not exceed 6V".

My question is if in addition to new charging logic only when PWML = 1 **also a voltage clamping mechanism that prevents the voltage between BST and SW from rising more than 6 V above?**What is meant by “electrostatic discharge (ESD)”, and how long does the additional mechanism (clamp) operate?

  1. Could you recommend an additional gate driver to MPQ1918 with 2 pwm inputs to switch a GaN FET half-bridge that comes in a non-BGA package?
  2. External diode is required between VCC and the BST input? If yes, so what the cause? I am asking because in the MPQ1918 datasheet, the application example shows an external diode being used.
  3. Is there a response time for the UVLO = Under-Voltage Lockout mechanism for both VCC and VBST?
2

Hi Yaki,

Thanks for reaching out to MPS.

  1. There is an ESD device between BST and SW pins. It operates like a zener diode as long as BST voltage is higher than 6V it will continue to discharge the cap. The device however can not be used as the main clamping mechanism for BST over-charging.
  2. MP1918 is in a QFN package, MP1916 is similar to MP1918 but in a BGA package.
  3. The external BST circuitry is not necessary, it’s just used in some applications like Class-D audio.
  4. The response time is not specified. Is there a specific response time you need?

Thanks,

George