The logic follows this sequence: Clear the Cause → Trigger the Reset. You must first ensure the Input Voltage is back to normal levels. Only then will writing a 1 to Reg 00h [7] successfully reset the FT pin and clear the internal fault flags."
I am writing now just to make the question clear again, as we have multiple exchanges in this thread.
Looking at the highlighted text below, how do we know that a fault status has been removed? Which register/bits give this information? Is it this register for example → GLOBAL_STATE_REPORT (05h) ?
Looking at the highlighted text above, which is the fault register that is referred in the text saying → “to clear the fault register”?
If over voltage condition is NO MORE present(active to inactive), the datasheet says that the corresponding channel turns back on → Does it mean the channel will turn back on without the need of WRITING 1 to register FT_PIN_MASK_CONTROL (00h) and bit 0?
I can help take over for Fox. I believe the latest image you sent 3 days ago is the correct datasheet text compared to the image in your original post (FLTCLR is bit[0], not bit[7]).
If VIN OVP fault occurs, then GLOBAL_STATE_REPORT (05h) will trigger and the channel shuts down. GLOBAL_STATE_REPORT (05h) is the fault register that is referred in your highlighted text.
Once VIN voltage goes back to normal, then the channel will turn back on. However, you need to manually clear FT by writing 1 to register FT_PIN_MASK_CONTROL (00h), bit[0] (the register does not automatically clear when VIN goes back to normal).
You can use the ADC register to check the VIN voltage to know when to clear register 00h.
Hello Rubas, thanks for the reply. I have some follow up questions.
What happens to the FT pin if I write 1 to register FT_PIN_MASK_CONTROL (00h), bit[0] - when the fault is still active? will the FT pin go HIGH for a short duration and again go back to LOW as the fault is still present? Or will the FT pin be continuously in LOW itself?
What happens to the GLOBAL_STATE_REPORT (05h) bits if I write 1 to register FT_PIN_MASK_CONTROL (00h), bit[0] - when the fault is still active? will the bits go to 0 for a short duration and again go back to 1 as the fault is still present? Or will the bits stay in 1 itself all the time, as the fault is still present?
How long (or how many ADC reads) we have to wait and monitor the ADC values to know that the fault is now inactive or not?
If we toggle the power on the ENable pin, do we have to configure the HSS again..?
If we toggle the power on the VINA or VINB pin, do we have to configure the HSS again..?
To know that the VINA/VINB over voltage fault is not present anymore, what is the expected voltage level in the ADC to look for, is it 16.5V? or 15.5V?
To know that the VINA/VINB UNDER voltage fault is not present anymore, what is the expected voltage level in the ADC to look for, is it 3.1V? or 4.1V?
To know that the OUTA/OUTB over voltage fault is not present anymore, what is the expected voltage level in the ADC, is it like VOUTx - VINx < 0.1V?
To know that the thermal shutdown fault is not present anymore, what is the expected temperature in the ADC to look for, is it 150 degree C?
If short-to-GND or current-limit protection occurs, the part latches off. To recover from this state, the device must clear the fault register and the FT pin by cycling the power on VINA or VINB, or by reasserting the EN pin. After doing that, if the fault is still present, the part will again latch-off. IS this correct?
