Why am I seeing so much noise on Vout ripple right at output capacitor? I’m measuring at Full BW on the free pads w/ the probe soldered on and target is 50mV and I’m seeing 120mV.
Based on measurement techniques typically done for power regulators, it is better to measure at a limited 20MHz BW due to high frequency signal artifacts possibly being picked up by the probe. Also, at Full BW, if the probe is near high switching transition areas, these can be picked up as well (i.e. Vin pulsating current if Vin caps are too close to Vout caps). It is best to orient the probe away from other components and not near high switching transition areas. Another way to assure yourself that the Vout ripple is actually lower is to check at the output caps close to the SoC being powered to see if this measurement is also exaggerated near the input of the SoC.