Hi expert,
I’m thinking about how intelli-phase can protect itself in OC and short test.
From your logic, positive current is only sensed from HS FET, negative current is sensed from LS FET, that’s okay but, HS FET will latch off, and report fault# flag after 4 cycles.
- If short happens across inductor(or SW to GND), current will ramp as fast as possible, any risk of so much delay for latch off actions & reporting?
- If short across SW to VIN, HS FET cannot see any over current, the LS FET will be burnt easily, right?