MP8017GL-Z (PSR Mode) - No PWM on SW Pin, Converter Does Not Start

DC-DC Power Converters
1

Hi everyone,

I am debugging a PoE flyback design using the MP8017GL-Z in Primary-Side Regulation (PSR) mode and would appreciate any suggestions.

Design Summary

  • Controller: MP8017GL-Z

  • Topology: Active Clamp Flyback (PSR)

  • Input: IEEE 802.3af PoE

  • Input Voltage: 51 V from PoE switch

  • Expected Output: 12 V

  • Transformer: EP475SG-10

  • Bias winding: Not used (PSR configuration)

The design closely follows the MP8017 PSR reference schematic in the datasheet.

Problem

The PoE interface powers up correctly, but the flyback converter never starts switching.

The SW pin remains at approximately 52.7 V DC with no PWM activity (verified using an oscilloscope).

The output voltage is only 3.67 V after the output Schottky diode.

  • Are there any common layout or component issues that can prevent the MP8017 from leaving startup in PSR mode?
  • Has anyone successfully used the EP475SG-10 transformer with the MP8017?

Any suggestions or debugging ideas would be greatly appreciated.

Thank you!

2

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A good place to start would be to check this with the typical application schematic. Does your schematic that you have match up with this?

Also, what is your expected load? This is defined for a 12V @ 1A output. The transformer you have chosen seems to be fine, no issues according to the following specs (assuming your load doesn’t exceed 2.1A):

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You mention that the SW node is ~52V. Is this waveform flat or is this seen as a square wave?

3

This is the layout as shown in the datasheet with the guidelines listed out below as well:

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  1. Keep the input switching loop between the flyback input capacitor, transformer, SW pin, and PGND as short as possible.

2. Keep the output loop between the rectifier diode, output capacitor, and transformer as short as possible.

3. Keep the active clamp loop between the active clamp capacitor, transformer, SW pin, and SNBR pin as short as possible.

4. Keep the input hot-swap loop between the PD input capacitor, VDD pin, VBUS pin, and VBUS capacitor as short as possible.

5. Place the VCC capacitor close to the VCC pin for optimal decoupling.

6. Ensure that the feedback trace is short and routed far away from noisy sources, such as SW.

7. Keep other signal leads (e.g. DET, CLASS, COMP, VDIODE, SS, and FSW) as short as possible.

8. Shorten the CP loop and BST loop for excellent hot-swap and HS-FET driver function.

9. Use a single-point connection between power GND and signal GND.

10. Place copper and vias under the MP8017 package for excellent thermal sinking.