MP8009a in SSR mode schematic check/help with debugging

[sander.vandriessche]

Good day,

I have integrated the MP8009a in an SSR forward topology. The circuit was based entirely on the example typical application from the datasheet. However, I am not able to obtain the 5V output on secondary side.

The circuit I have now, uses about 6mA on a 50V input. Every 320ms, the gate is driven by a 10Vpp pulse train for about 10ms. The resulting output is a rise in voltage to 2.2V which then quickly slopes down to 0 in the same 320ms timeframe.

Any help/advice would be greatly appreciated.

[Fox.FAE]

Hi Sander,

Can you share the layout with us? We can help you do a layout review to check whether there are any problems. Thanks!

Best,

Fox

[johnsonneil176]

@sander.vandriessche

Good day,

I have integrated the MP8009a in an SSR forward topology. The circuit was based entirely on the example typical application from the datasheet. However, I am not able to obtain the 5V output on secondary side.

The circuit I have now, uses about 6mA on a 50V input. Every 320ms, the gate is driven by a 10Vpp pulse train for about 10ms. The resulting output is a rise in voltage to 2.2V which then quickly slopes down to 0 in the same 320ms timeframe.

.

In SSR mode, layout and feedback routing are critical. I’d closely inspect compensation components and switching waveform integrity. If you’re driving loads like VN5025AJ-E downstream, transient spikes might influence regulation. Double-check grounding strategy and ensure your current sensing path is short and noise-free to avoid instability during switching transitions.

Any help/advice would be greatly appreciated.

In SSR mode, layout and feedback routing are critical. I’d closely inspect compensation components and switching waveform integrity.