I’m not sure whether the FB sampling is designed such that within one full cycle only one sample of the FB voltage is taken or further samples could be initiated. If the sampling cycle including the 300 ns blank time is just starting on any steep positive slope on the FB pin (normally, when the primary MOSFET is turned off), then a second positive slope on this pin within a PWM cycle could initiate another sampling which can be very inaccurate.
The reason of this question is following scenario: A Flyback topology where a secondary synchronous rectification using an SSR control IC is implemented. Under low load circumstances, the minimum ON time of the secondary MOSFET could result in (intended) current reversal while at the termination of SSR ON state, this current is then found as negative current (ramping to zero) in the primary MOSFET. At this time, the drain voltage goes quickly to zero (pseudo on via body diode), while - at the time that the primary drain current has zeroed - the voltage increases again. The same applies to the FB voltage. This could trigger a second sampling and hence, introduce an inaccurately sampled value.
Therefore the question: is it ensured that only one sampling takes place, controlled by the on to off state transition of the primary MOSFET?
Moreover, it’s interesting to know if the documented sampling time of up to 700 ns is meant as voltage averaging over this interval or as a single sample shot within this time interval.