MP6543HGL-B PCB layout

Good Morning,

I’d like to ask some additional information about the recommended PCB footprint and layout for your part number MP6543HGL-B; particularly, about the connection of the central exposed thermal pad; we purchased your evaluation board, and I see on the datasheet of the evaluation board that the only connection of the IC to GND is through the central exposed thermal pad; there’s no GND plane connections on the TOP layer; LSS pins (8,12) and pin 15 are connected to the central pad, and then there is a solder mask on the BOTTOM layer in correspondence of the central pad.
The question is: how is the central pad connected to the solder mask on the bottom layer? Particularly, which is the recommended number and sizes of the via holes to be placed under the central exposed thermal pad to efficiently perform the GND connection?

Thank you so much. Kind regards.

Hi a.rigoli,

Thank you for contacting the MPS Forum. The exposed pad is connected to the Bottom layer through vias. There are 8 vias (1279 mils, 1300 mils) on this pad. If you would like the device evaluation board layout, we can send you the Altium file if you contact


Good Morning,

thanks for the reply.

We don’t need the files of the layout of the ev board, thank you.

The info about the number and dimensions of the vias is sufficient.

Kind regards.

Can the datasheets for the MP6543* devices be updated to show the paddle as pin 25 and it being ground?

I just checked the datasheets and there is no mention of the thermal pad being ground.

Thank you!

Hi harjit,

While it is common practice, we agree that the exposed pad connection should still be directly stated in the datasheet. I’ll ask our product line for the update.

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