I’d like to ask some additional information about the recommended PCB footprint and layout for your part number MP6543HGL-B; particularly, about the connection of the central exposed thermal pad; we purchased your evaluation board, and I see on the datasheet of the evaluation board that the only connection of the IC to GND is through the central exposed thermal pad; there’s no GND plane connections on the TOP layer; LSS pins (8,12) and pin 15 are connected to the central pad, and then there is a solder mask on the BOTTOM layer in correspondence of the central pad.
The question is: how is the central pad connected to the solder mask on the bottom layer? Particularly, which is the recommended number and sizes of the via holes to be placed under the central exposed thermal pad to efficiently perform the GND connection?
Thank you so much. Kind regards.