[MP5990GMA-0000-Z] Soldermask and Pastemask issues in Non-VIPPO Design

DC-DC Power Converters
1

Hi MPS team,

We are working with the Fab house and encountered an issue with the soldermask and pastemask of the footprint, which were built based on the recommended footprint in the datasheet.

Currently, We apply Non-VIPPO for this design. Therefore, all the via will be plugged with solder mask including vias on FET SMD pads.

The picture below shows some green dots of soldermask (please see on the table) , and it would be placed on top of SMD pads.

We have modified the soldermask of the FETs to fit via plugging treatment. However, with the pastemask design, we are confusing between 2 options:

  • OP1: Keeping the pastemask as recommended in the datasheet will lead to solder being blocked by the soldermask of the vias (green dots in the picture above), due to reducing the pastemask ratio and it maybe cause thermal issues.

  • OP2: Modifying pastemask to avoid soldermask of the vias and improve pastemask ratio.

Please see table below for details.

We have 2 databases with different pastemask design:

  1. Plugged_Original_Pastemask: FETs are designed with Modified soldermask for Plugged via and Original paste mask as manufacturer’s recommendation.

  2. Plugged_Modified_Pastemask: FETs are designed with Modified soldermask for Plugged via and Modified paste mask to void soldermask dots and improve pastemask ratio.

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Could you help to review and give us an advice if there are any issues or potential risks.

2

Hello,

The second option that you have listed is probably the better approach if you are able to validate the pastemark design that you have with a simulation or perhaps even prototyping. The benefits of this option over option include:

  • Increased solder coverage will yield improved thermal performance, which would also in turn reduce long term thermal stress.
  • Ensures that you are avoiding solder blockage solder obstructions by the solder mask over the vias on the PCB.

Of course, Option 2 only works assuming that you have the ability to collaborate with the fab house and if you are also able to test any prototypes to confirm there are no issues with the soldering process.

If this isn’t possible, then sticking with Option 1 incurs less risk and you would be aligned with MPS manufacturing recommendations. Hopefully this provided some insight to your issue.

Best,
Krishan

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