I am designing the power supply with 14v output voltage and up to 5A current but there is a problem that output voltage heavily depends on the load current and changes as much as by 1V.
At the higher currents pretty high PWM jitter is observable.
What can be causing this problem?
My PCB is not as compact as suggested in the datasheet to improve thermal performance (inductor is moved slightly further away from the IC because it gets very hot.) and electrolytic capacitors are used for both input and output. which should be better for this chip
External Ramp Compensation uses DC Blocking Capacitor (0.1uf)
Just some guy on the internet here, but I suspect that the inductor is saturating. Inductors have several current ratings, the most critical is the saturation current rating. Once the inductor saturates, all the little magnetic domains in the iron are lined up in one direction and it effectively looks like air at that point as far as magnetic properties go. The value of the inductor falls to a low value, the current in the inductor shoots up, the chip current limit reacts duty cycle pulls in and the output voltage falls. You need an inductor with a saturation rating of 7A or higher. There are many other possibilities good luck
Yes, I also suspected that too, because jitter is a very common consequence of inductor saturation but replacing the inductor with something of double rating did not change anything.
The strange thing is that this design more or less worked fine but no longer works after PCB redesign for the better thermal performance and replacing ceramic capacitors with electrolytic
Well that would tempt me to go back to the ceramics. The whole using the ESR of the output cap strikes me as troublesome. How stable is that parameter? I am pretty sure it varies with temperature quite a bit in an electrolytic. If you use a ceramic with essentially zero ESR and then add in the ramp signal you need as shown in the data sheet you have pretty precise and temperature stable control of the situation.
According to the datasheet, high ESR is preferable for this IC because it needs output ripple to operate properly which was one of the reasons to choose electrolytic capacitor and it happens that 1000uF electrolytic capacitor is even cheaper than 10uf ceramic at the required 24V voltage.
But actually, I tried that too, adding extra ceramic caps does not help.
I would try to get an eval board and then slowly evolve it to your circuit. The nice thing is you have two layouts to play with. Same components different result with a layout change might mean something you changed mattered, or it might mean something got goofed up i.e a net got dropped. I wouldn’t thing that extra trace length in series with the inductor is important that just adds free extra inductance. A larger area of switch node might couple signals into a sensitive node. The datasheet seems to suggest that no matter what you want ceramic input caps. What is your Vin? Are you sure it isn’t dropping under load. That datasheet seems to imply that some jitter is inevitable still regulation should be good.
My Vin is very wide range starting from nearly Vout to the 35V. output also should be selectable between 14 and 28v options.
Evaluation board is not a viable option because it is designed for only 3.3v output only.
What could be affecting all this instability may be the fact that my new board has a pretty big plane connected to the output switch to move away from from the heat from IC and this somehow can inject something into the feedback pin.
But still, the main question remains why output voltage is so extremely unstable
It so not just dropping under load, it is actually increasing under load to some extent then is starts dropping.
Inductor value is 15 uh situation with frequency setting resistor is strange if I set it too low and frequency goes above 600khz everything stops working regardless of any other parameters
it only somewhat works if I set frequency very low and then leave everything to that RC compensation circuit.
Well to maximize your dropout performance Vin=Vout you should be operating as slow as possible. I swag 720k for the frequency resistor. Coupling from the SW node to the FB node seems like it could well be a problem. I don’t notice a spec on hysteresis on the FB pin. In any case once tripped it turns the SW ON for a fixed time. Once the ON time has run you get a negative going dv/dt at the SW node if there is capacitance to the FB node the dv/dt could I suppose retrigger the system. I think the symptom would be a lot of minimum off time pulses with Vout building higher and higher until eventually vout was too high and the edge wouldn’t retrigger the system. So then you would have a long period of nothing until Vout decayed enough to retrigger the FB pin, followed by a repeat performance. Have you scoped the FB pin? I would maybe try a biggish cap Vout to FB to try to shunt the noise away from the FB pin.