MP2722 battery missing behaviour under Vsys load

Battery Management
1

Hello,

I am testing MP2722 behavior in my prototype and I would like to confirm whether what I observe is normal.

In my design, SYS is loaded and powers some peripherals. While USB-C input is present and the battery is being charged, I physically disconnect the battery positive terminal (VBATT). GND and NTC remain connected.

In this situation:

  • the charger still seems to indicate charging,

  • and I still measure about 4.2 V on the BATT node, which looks like the battery charging voltage.

Only when I put my peripherals to sleep does the MP2722 start reporting the expected battery-missing condition.

Is this normal behavior for MP2722?
Can the charger keep the BATT node at around the regulation/charge voltage even when the battery positive terminal is physically disconnected, especially while SYS is loaded?

Thank you.

2

Hi Dawid,

This behavior is normal and expected for the MP2722: in a heavy SYS load condition, the DC/DC regulation loop can “mask” the chip’s internal battery-missing detection pulses, but once the load drops and the IC goes to Sleep Mode, the chip can successfully pull down the BATT node to confirm the battery is absent and report the status. Please let me know if you have any other questions.

Best,

Fox