MP2672 getting above 100°C while charging

Battery Management
1

Hello,

I’m working a project, where I would like to use the MP2672 to charge two 18650 cells in series. My problem is that MP2672 gets hot quickly (in 2-3 seconds to above 100°C) even though I’ve set the charge current to 500mA.

Here is the schema:

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I’m aware that C14 is at the wrong place, it should be between IN and GND. This is due to an error in the original schema which I had to work around but I would not expect this to be the cause?

V_IN is attached to a 5V USB-C Notebook charger. It should be able to provide enough current. V_BATT and V_SYS are connected to a disabled circuit.
The solder bridge JP3 is closed connecting the 24k resistor to ISET which should give a charge current of 500mA. ACOK and STAT are connected to two LEDs. Both of them are solid on as soon as V_IN is connected.

This is the inductor I’m using: https://jlcpcb.com/partdetail/Sunlord-MWSA0603S1R5MT/C408444

If the batteries are not in place, MP2672 gets to about 30°C. As soon as the batteries are connected, it heats up quickly to above 100°C. The heating also happens If I add a load (< 500mA) to V_SYS without batteries installed.

I’ve already compared my schema with the reference design but could not find the error. The same issue happens on two different PCBs.

Since I’m a hobbyist engineer, I’m a bit lost on how to further debug this. Would be great, If someone could guide me to the right direction.

2

Here is also the layout of the PCB around the charger:

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Probably not optimal but hopefully good enough to not cause such an issue.

3

One additional remark:

I have left pin 12 (SW) unconnected and only used SW on pin 2. The datasheet seems to do the same in the reference layout:

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Is this ok?

4

Au Contraire, I do expect it to be the cause. That will cause massive switching loss in the FET at least get rid of C14 and see what happens. Plus do you have a EVAL board? These are super useful tools I know they are expensive but how much are you spending now?

5

Yeah thank you very much. This indeed was the issue :slight_smile: No, I don’t have an eval board. Currently, it looks like my issues with this IC are solved. If not, I might look into one.

6

You should really look at a common GND. The Chip, The output caps… same piece of copper. Look at the snippet below… Also 3 capacitors → 3 vias minimum and route the skinny track outside the GNDS - straight line connections between input, output and chip

7

Thanks for your input. I have already adapted my layout to match more the one in the datasheet:

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I’m not sure what you mean with skinny track outside the GNDS and the straight line? Is this already solved with the new layout?