I am incorporating the MP1918 driver into my design to drive a GaN Half-Bridge stage.
I would like to understand precisely what happens inside the device when the driver is powered off or without a supply voltage (a state where VCC is absent or equal to 0V).
I have a few questions regarding the behavior of the gate drive outputs (HGN/LGN) and the internal sink FETs:
State of Internal Sink FETs: When the driver is completely off (VCC = 0V), what is the exact state of the internal sink FETs (connected to the HGN and LGN pins)? Are they in a low-impedance/conductive state or in an open/high-impedance state?
Low Impedance / Short Circuit between VG and VS: When unpowered, does the driver guarantee a low-impedance path (short circuit) between the Gate and Source (VG to VS) of the external GaN FETs for both the High-Side and Low-Side?
Internal Mechanism without Supply Voltage: If a short circuit / low-impedance path between VG and VS does occur while the driver is off, how is this achieved internally within the IC in the absence of an active VCC supply voltage to turn on the internal sink FET?
I would greatly appreciate your clarification on this topic.
when the device is powered off, or VCC = 0, then nothing is powered so no FET (inside or outside) can be enabled. As per the datasheet, all gate driver outputs are OFF when VCC < VCC_UVLO. This means the gate drive is HiZ so the GaN FET gates would be floating. Once VCC goes past the different UVLOs, then the gate drive outputs become enabled and follow the PWM inputs. Do note that in the case that VCC is less than the bootstrap UVLO, then only the low side gate drivers follow the respective PWM input. I think this also answers question 2 and 3. In essence, when there is no power there is just no way to drive the external GaN transistors to be in the OFF state, as that would require the negative side gate drivers to be powered. Hope that makes sense!
Thank you for your reference to the answer. I did not understand your answer, because in the specification of MP1918GQE in the section talking about - Under-Voltage Lockout (UVLO) and in Table number 2 - it is written that when the driver component is not fed with supply voltage when VCC<VCCTH the HG and LG in LOW and not in Hiz mode according to your answer.
If the driver’s lower FET is low, will it be possible for the gate and source potentials of the off GaN to be equal?
Therefore, I would really like you to clarify the operation of the driver when no supply voltage is provided to the component. I am trying to understand the details because I chose to integrate the MP1918 into a power board with GaN FET components connected in a half-bridge configuration to switch a brushless motor.
This topic is important for my design, so I would appreciate a detailed answer.
Just wanted to follow up with you, I do believe that the MP1918 should be able to drive both high side and low side gates to GND in a powered off state as per table 2. However, we are trying to get a MP1918 unit in our labs to validate this power off behavior to confirm.
I have confirmed in lab that while there is no power applied to the MP1918, there is a low impedance path from HG to SW, and LG to GND. The GaN FETs you are driving will be forced into the off state when the MP1918 is powered off.
In the powered off state, the MP1918 exhibits a diode like IV curve from LG to GND, with the turn on voltage around 0.75V. The same goes for HG to SW.
Let me know if you need additional information about this part.
First, thank you for your help and the detailed answer.
Could I get an internal schematic of the component? I would like to understand electrically, at the chip level, how a low impedance is maintained between HG and SW and between LG and GND when there is no power supply to the IC. If I understand correctly, once the VCC voltage rises above the threshold, this low impedance no longer exists?
I am asking these questions to understand how the power board I am designing will operate. It consists of a 3-phase half-bridge topology built with EPC GaN FETs (EPC2361), where each phase leg is driven by an MP1918 gate driver. The load connected between the phases is a 3-phase brushless DC motor. I want to evaluate a scenario involving Back EMF, where the motor might be rotated by an external force. This rotation will generate a voltage at the switching node between the two GaN FETs in the half brigde. In such a scenario, the GaN devices need to enter reverse conduction, which occurs when VG and VS are at the same potential, resulting in a VGD (Gate-Drain voltage) greater than the threshold voltage. From this description, you can understand why it is critical for me to know how the gate driver operates electrically and how this internal low impedance is achieved within the device. I would greatly appreciate an internal diagram or schematic illustrating this.
Unfortunately, we cannot share more detailed internal schematics of the MP1918. However, what I can do more testing on our EVB in the lab to ensure that stray positive and negative voltages at the output of the half bridge do not cause issues with the board.
Let me know if you want me to run additional tests to get the information you need
I did some more lab measurements. As soon as the chip is turned on, the output become either driven high or low. No need to worry about floating outputs here. Any back EMF should also be absorbed by the supply rail assuming that you have adequate clamping protections.
In the power off state, I applied 50mA of reverse current across the output of the half bridge to ground. This result in the output of the half bridge measuring -1.8V. HG measured -1.8V, and LG measure -.056V with respect to GND. VIN (supply of half bridge) measured to be 0.1V, and the VCC (gate driver supply) measured to be -.371V.
Hope this helps. Let me know if you need additional support.
Thanks for offering to test this on the EVB. To help us evaluate potential reverse conduction and gate-floating conditions on the GaN FETs during Back-EMF events when the driver is unpowered, could you please perform the following tests on the MP1918 EVB:
Measure the impedance/resistance between HGN, HGP, and the source midpoint node of the half-bridge (high-side GaN FET source).
Measure the resistance between HGN, HGP, and the SW pin of the driver.
Measure the resistance between LGP, LGN, and the driver’s PGND pin.
2. Internal Diode Mapping:
Map all internal ESD or clamping diodes between the driver pins (HGP, HGN, LGP, LGN, SW, BST, PGND, VCC).
Please specify pin connections for anode/cathode for each internal diode, and explain their intended functionality (e.g., ESD protection, internal bootstrap circuit, or output clamping).
3. External Voltage Injection Test at Half-Bridge Midpoint VCC =0v, VIN = 0V:
Inject a DC voltage of 5V directly at the output/midpoint node of the half-bridge (high-side GaN source / SW node).
Measure the resulting gate-to-ground voltage VG and gate-to-drain voltage VGD on the high-side GaN FET.
Measure the voltage appearing at the VIN node as a result of this injection.
Confirm whether reverse conduction occurs through the top GaN FET under these conditions
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