Minimum clearance for High speed signals from inductors

Inductors
1

Hi,
We are using P/N MPL- AL6050-1R2 in our design. Could you let us know how far should we space the PCIE signals (on top layer) away from the body of inductor on the top layer.

Thank You,
Ravi

2

Hi Ravi,

Sorry, but we do not have any general guidance for inductor clearance to the PCIe lines. It would depend on the current through the device, if the PCIe lines are differential or not, etc.

Regards,
Vinh Tran

3

Hi Vinh,
Thank You for the quick response.
If there is an information regarding magnetic flux vs distance from the inductor could you please share.

Thank You,
Ravi

4

Hi Ravi,

Our molded inductors are fully shielded. So, there is no magnetic flux.

Regards,
Vinh Tran

5

You may want to follow the general rules for a High Speed Differential Pair (3 x track width). Ensure there is a GND fill between the magnetic device and the Differential pair (at least 3 x track width).
If you really want to work it out, you are going to have to talk to a RF engineer and borrow his/her time / tools.
Note: you can do the same with a strip line trace, but ensure the GND return follows the trace and can’t go under the inductor.

Simon