Hello,
While reviewing the MBM14S-P100 evaluation board, I noticed that the documentation specifies:
However, the board uses 10 x IAUS300N08S5N011TATMA1 MOSFETs, each of which is rated for a continuous drain current between 123A and 300A, depending on conditions.
My questions are:
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Why is the board limited to 100A continuous and 150A peak current, even though the individual MOSFETs can handle much higher currents?
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Why are 10 MOSFETs used in parallel? On paper, 2 or 3 devices should be sufficient to reach the specified 100–150A.
Thank you in advance for your clarification.
Apologies for the late response here. I will review these questions with the BMS PLs and get back to you soon.
Hello again, I am back with the BMS PL’s feedback to your questions.
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The margin of safety for keeping the MOSFETs within SOA increases as the number of MOSFETs in parallel increases. This is because, very small differences in layout and MOSFET tolerances will create some imbalance in consumption between devices. Conditions in which FETs can support higher currents are very unreal. Datasheets show the currents that the FETs can handle in a very unrealistic design/layout (no other FETs/components nearby, super thick copper layers, etc). Furthermore as mentioned earlier, the current is not linear to the FETs you put due to the temperature increase and temperature radiation to other nearby FETs. So adding an extra FETs does not multiply the current by 2 essentially, it is like a negative parabolic curve.
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Thermal conductance will ultimately limit how much power can be delivered. With heat sinks and other thermal management, I think we can support higher continuous current. We use 7 in parallel in the latest design and even though we use that there is a 40-50ºC temperature increment. So, we are using the minimum possible already.
Please let me know if there are any further questions that you may have.
Best,
Krishan