We are interested in using the MPM3833 to supply 1.2V core power (from 3.6V) to an FPGA, one application it is recommended for. However to keep impedance low the FPGA manufacturer recommends about 500 uF of total capacitance and the MPM3833 datasheet indicates the maximum Cout is 100uF. My questions are: what are the concerns with using that much output capacitance, do you recommend a way to compensate, and do you recommend not using this part for this application?
Welcome to the forum.
The MPM3833 can definitely be used for your application. The output capacitance if chosen higher than 100uF, can result in instability of the voltage regulator. It is recommended to use 22uF, but if you want to keep the impedance low, I would suggest to use an LC filter at the output and then you can add more output capacitors. The extra inductor or choke will prevent the extra caps affecting the regulator’s loop.
Doing this, we don’t guarantee the output ripple spec. So, it would merely be a trade off.
Thanks but I would like to avoid doing that that for size and output ripple reasons. I simulated with MPSmart. Start-up seems fine with >100uF output capacitance but 3A load transient does indeed become unstable, and you can’t even get to 100uF if the additional capacitor(s) have higher ESR. I found if I stick with all low ESR caps I can go up to 180uF (without margin) so I figure I’ll stick with all ceramics. I will test with an evaluation board but does this agree with your understanding?
The MPSmart results can be different from the real life scenarios. But, you can try out with the EVB and check how the 180uF output capacitance plays out.