Hello,
I was reading one document to check inductor and IC compatibility of MPS and got doubt regarding buck converter. below is the link
It says that ‘By comparing the DC resistance (RDC) of the inductor with the RDS(ON) of our MOSFETs, we can use the fraction of the RDS(ON) for matching. Both terms (RDC) and (DC x RDS(ON)) should be close to one another. They don’t need to be perfectly equal, but we can see the optimal efficiency with close terms (within mΩ).’
Can you please explain how efficiency is improved when DCR and RDS on value is close.
Thanks,
AZIZ
Hello Aziz,
This is a good question. Of course, minimizing the DCR and RDSon of your FETs and Inductor when designing a buck would certainly maximize efficiency as well as minimizing the losses. The lower the value across the board, the better. Of course, this is where cost becomes a limiting factor.
However, in the example that you linked, the low-side FET was conducting roughly ~80% of the time where the high-side FET would be conducting ~20% of the time as this is dictated by the Duty Cycle = Vout / Vin for a buck.
Therefore, a lower RDSon for the low-side FET is the logical design choice. Given the ratio difference between the high-side and low-side RDSon, this can determine how to choose the DCR. When RHS≈RLS≈RDCR, the total conduction resistance is minimized for a given inductor value.
This means the power dissipated in the switch stage is roughly proportional to IL2×RDCR, which is the same as if the MOSFETs had zero resistance. This is the most efficient configuration as is what is meant by the author.
Matching or closely matching the RDSon of the high- and low-side MOSFETs to the inductor’s DCR ensures that the inductor’s resistance is the dominant conduction loss, minimizing total switch-stage losses and maximizing buck converter efficiency. If you check nearly any buck datasheet, you’ll notice the RDSon of the high / low side FETs can vary, but not by too much.
I hope this provided some insight.
Best,
Krishan