EV6925-S-00A specifications conditions and methods

Dear Supportmember,

I am considering EV6925-S-00A.
I have a question.

(Specifications Conditions)
Output voltage 42V
Output current 5A

Q1
Can the output voltage of 42V and output current of 5A be used on the evaluation board of EV6925-S-00A?

Q2
Vdd is separated from Vout and 13V is supplied from the outside from another power supply.
Is there any problem with this usage?

Best regard.

Dear Supportmember,

How is the progress?

I have add a Q3 Question.

(Specifications Conditions)
Output voltage 42V
Output current 5A

Q1
Can the output voltage of 42V and output current of 5A be used on the evaluation board of EV6925-S-00A?

Q2
Vdd is separated from Vout and 13V is supplied from the outside from another power supply.
Is there any problem with this usage?

Q3
If the operation is overcurrent,
Can MP6925 detect and stop?

Best regard.

Dear Supportmember,

How is the progress?
My customer is waiting Supportmember answer.

Best regard.

Hi Hideyuki,

Q1) The output caps on the EVM, C2, C3 and C4 are 35V caps. They have to be changed to higher than 42V caps for maximum cap voltage reasons. You can maybe swap out with 50V or 63V caps. Also Mosfets M1 and M2 are not rated for 42V Output. You will need to use 120V or 150V mosfets since each mosfet will have at least 84V across it and that is not including the spike during switching transitions. Same with caps C1 and C5. It is better use slightly higher voltage caps there also.

Q2) It is OK to apply separate Vdd of 13V as long as it is isolated from HV Primary side Input and can be referenced to the 42V Output’s Ground.
Please make sure that the external bias of 13V is always present and is never locked off under any condition. If it gets locked off then, it is needed to make sure that the LLC primarily controller gets turned off as soon as the 13V goes down. If this does not happen, then the Secondary mosfets can get damaged due to thermal runaway.
Another option is you can always use a linear regulator from the 42V Output to generate the 12V bias and use diode Oring between this 12V and the external 13V. So 2 additional diodes will be necessary along with a linear regulator. This will prevent the above condition from happening.

Q3) Even if there was a current sense and the MP6925 could actually turn the gate off, the internal diodes of the Mosfet would still conduct into a short or a overcurrent load as there is no way to control them. So it does not help in having a OC protection on the MP6925. It is better to turn off the Primary side LLC controller. Check out our LLC controllers like HR1211 or the HR1001x product family.

So it is not useful to have the overcurrent protection in MP6925 because of the following conditions:

  • Internal Body diode of the Secondary mosfet fails as a short or,
  • The Output Load is short circuited or overloaded. The Internal Body diode of the Mosfet will still conduct into the short even if we pull the Gate of the secondary mosfet low.

We also have current sensors, they can be used to sense the current and send a signal to the primary side through an opto–coupler to shut down the primary side controller.

Dear Sunandhitha,
Thank you very much for your answer.

I have a add Question.

Q4
There is a phenomenon that the gate voltage time becomes shorter when a output current is increases.

(Situation)
With no output current, the gate voltage waveform was 1.6 μs at 8 V.
When the output current was increased, the gate voltage waveform was shortened to 0.4 μs at 10 V.

What could be the cause?

Best regard.

Dear Sunandhitha,
How is the progress?

Best regard.

Hi Hideyuki,

The gate waveform of SR Mosfet is dependent on the Primary side gate waveform of the LLC. This primary side LLC controller makes the gate ON time decision. The MP6925 just initiates its gate drive pulse depending on this gate waveform of the primary LLC controller. Also the LLC controller is a frequency modulated controller and not duty cycle modulated controller which is the case for non-resonant hard switched converters. So duty cycle comparison is not a good measure. The switching frequency should be measured at both the load conditions.

Consider our LLC controllers such as HR1001C and HR1211.

What is switching frequency measured at full load and no load and also at the load when the gate waveform has ON time of 0.4usecs at 10V output? What is the load current at this condition?

Dear Sunandhitha,

Thank you very much for your answer.

When the gate waveform has ON time of 0.4usecs at 10V output,
switching frequency is 178kHz.
The output current value is 1 to 2A.

It is not measured at full load.

When there is no load, the switching frequency is 200kHz.

Best regard.

Hi Hideyuki,

Depending on the load condition the device would vary the switching frequency and once it is in light load, the switching frequency varies drastically to support the load condition.

Dear Sunandhitha,

Thank you very much for your answer.

I have add a question.

Q5
After checking the gate voltage waveform on the primary side, it was operating at a constant switching cycle.
Only the SR MOSFET gate waveform of MP6925 is shortened.
Is there a possible cause?

Best regard.

Dear Sunandhitha,
How is the progress?

I’m confused because the gate driver on the primary side of LLC and the gate of MP6925 behave differently.

Best regard.

Hi Hideyuki,

Thank you for your patience.
There are two delays that are reducing the duty of the SR Mosfets compared to the primary Mosfet duty. These delays are shown below. When the drain starts to fall, the Mosfet on primary is OFF . As the load goes light, the fall in voltage you see in Vds waveform goes less steep because the dv/dt can be much lower. So the body diode of the SR Mosfets conduct much later and the gate to SR Mosfet turns on also much later than when it would normally at full load. So that delays the turn on of the SR Mosfet. Also since the current in secondary SR Mosfet is very low the turn off starts earlier than normal operation since the Vfwd voltage is reached sooner. See diagram below from MP6925 datasheet. At light load the % reduction of these two effects can be significant. So it will appear that the duty of the SR Mosfet is lower than the Primary FET duty. Also since the load is so light the benefit gained from keeping the SR Mosfet in ON condition is much lower. These delays are there to prevent shoot through situations where the mosfet that should be OFF continues to stay on. These protective delays can appear significant in light load but that has very little impact on efficiency since the load is so light that the benefit gained from keeping the Mosfet on versus body diode conduction is very small.

Dear Sunandhitha,

Thank you very much for your answer.

The answer me received is I think this is the operation when the output current becomes lighter.

This phenomenon is happening, this is when the output current becomes large.

when the output current increases, the gate voltage waveform on the primary side operates in a constant switching cycle, and only the SR MOSFET gate waveform of the MP6925 is shortened.

IIs there a anything else possible cause?

Best regard.

Hi Hideyuki,

Please make sure that the layout is as per what is shown in the datasheet. Please see below:

Also the SR duty will always be smaller than the Mosfet duty due to the blanking time at turn on such as below:
image

Also at turn off the gate voltage starts to drop as soon as the drop across the drain source goes below the threshold limit, Vfwd. Both of these delays are to prevent shoot through. So the SR duty will always be less than the Primary mosfet duty.
image

Dear Sunandhitha,

Thank you very much for your answer.
We will send you the waveform of the evaluation board, could you check it?

happening phenomenon

・There is no gate waveform.
・ALL turn-Off is generally slow.
・The timing when the gate drive should not come out comes out.

Is there a anything else possible cause?
Best regard.

Dear Sunandhitha,
How is the progress?

Best regard.

Hi Hideyuki,

Looks like one of our local FAE is helping out with this particular issue. So I am going to be closing this post.