Can MPQ5850-AEC1 be used with multiple N-MOSFETS?

Hello,

I would like to create reverse polarity solution for high current consumption product estimated at around 80A maximum continuous current. Is MPQ5850-AEC1 able to drive multiple mosfets to allow high current pass-through? Is the gate driving current only limitation?

Kind regards
KP

Internet rando, but no it won’t work. The FET is operated in a linear mode with 20mV of forward drop. Put two fets in parallel and one of them will have a lower threshold voltage and begin conducting first. They won’t share current nearly as well as you hope. Use a bigger FET

Or get an EVAL board and try it, big big fan of EVAL boards

Everything that jshannon said is correct. The internal gate driver of the MPQ5850 is designed to drive a MOSFET for reverse polarity protection, but using multiple in parallel to achieve 80A would require careful consideration of the gate charge on all MOSFETs combined. Also, you would need to ensure that the driver is able to operate at various loading conditions that reflect your application, so getting an EVN would be good to test this. Any parasitic elements could disrupt even current sharing as well which would therein lead to thermal stress, so thermal management is key assuming you move forward with testing.

If multiple parallel FETs are required for your application, then it would certainly be worth using an external gate driver. But getting a higher rated FET would certainly be the simpler solution here.

Not to rain on your parade, but that won’t work either. This operates in a linear mode, the FET is turned on just enough to achieve 20mv of forward drop. So the gate voltage is going to be at the threshold voltage plus whatever extra is needed to drop the voltage drain/source to 20mv. Threshold voltage between mosfets varies by a bunch, and it drops as the fet warms up. Two separate ideal diodes in parallel might work but even there, one of them would servo to 20mV and the other would servo to 19 and hog all the current initially.

This is fair. I suppose it was worth mentioning assuming that Karol did decide to test with an EVB.

From what I can understand from datasheet, correct me If I’m wrong, it says that operation in linear region and 20mV drop regulation, will only be performed for light loads (Iload * Rds(on) < Vsd). In case of light load even if only one MOSFET takes whole load it’s not an issue. With higher loads MOSFET works in full saturation.

Well it attempts to hold 20mV and as the current increases the gate drive increases. eventually the FET would be fully on 10V and any parallel fet as well. So I guess the pessimistic engineer would go look at a FET and suppose that she had one FET with minimum threshold and one with maximum threshold and then figure out how much current the easy to turn on FET will be at before the reluctant fet begins to turn on. The other way to look at it would be how much dissipation do I have in the easy FET at 21mV across it, at which point the gate drive will rail?
If we hold the FET to say 1W of dissipation 21mV is 50A so that is quite a lot of current.

So I now think you are correct, they won’t share exactly but it doesn’t matter.

I will try to perform some testing with custom EVB and will share a results.

Thank you, for your input!