AX5688 application manual, hardware manual or reference design

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1

Hi MPS-Team,

I’m looking forward to design a Class-D Amp based on the AX5688.
It’s hard to do it with only the datasheet available on the MPS site alone.
Some info regarding schematic recommendations would be great to get startet.
Are there some application manuals or hardware manuals that can be provided?
Especially for the ADC feedback input filter recommendations.

Also, what are the benefits of running the chip in PBTL mode in comparison to just BTL mode?

Best regards,
David

2

Hi MPS-Team,

additional question, how to connect INRP and INRM. In older demo schematics from Axign I saw just a resistor to ground per pin. Is that still the case and which value to choose here?

Best regards,
David

3

Hello David, apologies for the delayed response:

For any design resources that are not outlined in the AX5688 datasheet, please contact MPS NOW Remote Support - Support for more immediate support. But I can answer you second question based off of the AX5688 datasheet:

  1. PBTL (Parallel Bridge Tied Load) from general config:
  • PBTL connects connects two amplifier channels in parallel to drive a single low-impedance speaker.
  • This would increase current capacity and enable a higher power output as a result.
  • This is optimized for high power, single speaker setups
  1. BTL (Bridge Tied Load) according to the datasheet:
  • Uses two channels differentially to drive a speaker where the voltage swing across the load is doubled as a result, providing efficient operation for standard impedance speakers.
  • Suited for stereo systems or any moderate power applications.

Hopefully this provided some insight.

Best,
Krishan

4

These pins if unused would be tied to GND with a 10k or 100k Ohm resistor.

If INRP and INRM are used, then they should be connected in differential mode to the audio signal source directly. In single-ended mode, only INRP or INRM is connected to the signal source while the unused pin is pulled down to GND.

Please refer to the datasheet for any more details on these pins.

Best,
Krishan

5

Hi Krishan,

thank you for your support on that matter. I’ll contact the support if there are any open questions regarding supporting documents and more info on that part.

Best regards,
David

6

Ok thank you for the clarification, I was confused because the chip block diagram shows them directly connected to the internal reference and biasing circuit. If further questions arise here I’ll go through MPS NOW as you advised.

Best regards,
David