I noticed something bothersome about the SW of the power supply circuit that uses MP2908 to make DC24V from DC48V.
The lower limit of the SW waveform was about -1V.
I think this is related to the characteristics of the switching FET or diode, but what do you think the cause is?
The circuit diagram is based on the typical application circuit in the data sheet, but I changed the output voltage, etc. The FET used is STL7N6F7, and D is DFLS1150-7.
Thank you.
Waveform
CH1: Unused
CH2: SW Voltage [V]
CH3: Load Current [A]
Hi Yuki,
The lower limit of the SW waveform should be negative.
In this figure, for the off-state situation, V_A=0, and there is a voltage drop of diode. And it is the same with MOSFET. MOSFET has a Rds_on which will also cause a voltage drop.
And from the datasheet of DFLS1150-7,
Vf = 0.82V when If =1A. In your application, maybe Vf is close to 1V, which make the -1V at SW reasonable.
Sincerely,
Fox
Thank you for your quick reply.
I understand why SW is about -1V.
However, the absolute maximum rating of the MP2908 is -0.3V to 65V, so I think the current state is over the rated value.
The current circuit uses the DFLS1150-7 that was on the Typical application circuit.
Do you think changing the diode is a good idea to reduce this undershoot?
Hi Yuki,
I got your point. From the circuit in the datasheet of MP2908, the voltage should not reach -1V. You can try to follow the BOM of the datasheet of EV2908A-F-02A. Change the MOSFET is the key to lower the absolute value of SW voltage.
Sincerely,
Fox
Hi, Fox
Your hint helped me find the cause.
It seems that the Vds of the current FET is not small enough.
So I checked the BG voltage and it was driven at about 5V.
Is this voltage as expected?
If so, I would like to select a FET that can be driven sufficiently by this gate voltage.
Thank you.
Hi Yuki,
BG voltage should be lower than VCC1+0.3V. Test the voltage of VCC1 pin and get the answer. I think it should be OK.
Changing the FET can definitely solve this problem.
Sincerely,
Fox
Hi, Fox.
With your help, I was able to completely understand this problem.
I’m sure this can be resolved.
The only thing left to do is find a good FET, so we will consider it.
Thank you very much for your cooperation thus far.
Hi Yuki,
No problem. Let me know if you have any other questions.
Sincerely,
Fox
Not to harsh anybodies mellow here, but this is a problem with pretty much every switching regulators datasheet ever written, and occasionally observant engineers detect it. The little spikes of negative voltage at the switch node are created by the freewheeling current in the inductor flowing in the body diode of the FET, i.e before the FET is ON. This problem can be improved in terms of time duration by more precise timing of the gate drive pulse, but if you go too far then you risk having both the upper and lower FETs on at the same time. Which means cross conduction and a huge hit in efficiency. So the controller chip is designed with some dead time between the upper drive and the lower drive. If this really bugs you, you can slap a schottky diode in parallel with the FET and that will diminish the amplitude of the negative spike, but not its duration. A faster switching FET might diminish the duration a tiny bit but it is inherent in the controller design.
The correct “fix” is to either ignore it or get MPS and Analog and TI and… to rewrite their datasheets to reflect the actual operations of their IC’s and state that the SW node can go to -1.4V (or whatever) for up to 75nsec ( or whatever) and then you would have the happy situation where the circuit works and nothing in the datasheet is violated while the circuit works.
Good luck with that.
